Hysteresis modeling in graphene field effect transistors
نویسندگان
چکیده
Graphene field effect transistors with an Al2O3 gate dielectric are fabricated on H-intercalated bilayer graphene grown on semi-insulating 4H-SiC by chemical vapour deposition. DC measurements of the gate voltage vg versus the drain current id reveal a severe hysteresis of clockwise orientation. A capacitive model is used to derive the relationship between the applied gate voltage and the Fermi energy. The electron transport equations are then used to calculate the drain current for a given applied gate voltage. The hysteresis in measured data is then modeled via a modified Preisach kernel. VC 2015 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4913209]
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